Synopsys Design Compiler Tutorial 2021

set tech_lib /proj/tech_libs/90nm/typical set target_library $tech_lib/ss_0.9v_125c.db set link_library [list * $target_library $tech_lib/memory_compiler.db] set symbol_library $tech_lib/symbols.sdb

The synthetic_library for DesignWare is crucial. If you miss this, your multiplier or ALU synthesis will fail. synopsys design compiler tutorial 2021

# Input path: data arrives 0.6ns after clock edge set_input_delay -max 0.6 -clock core_clk [get_ports din*] set_input_delay -min 0.1 -clock core_clk [get_ports din*] or SystemVerilog. For 2021

# ------------------------------------------------------ # 1. Read and Elaborate RTL # ------------------------------------------------------ # Clear previous design remove_design -all read_verilog and read_vhdl are stable

You can read Verilog, VHDL, or SystemVerilog. For 2021, read_verilog and read_vhdl are stable, but the recommended TCL command is read_file .