Page through the "PCB Guidelines" (often in an appendix or referenced application note). The v2.5 spec emphasizes:
At its core, the D-PHY is a source-synchronous, physical layer (PHY) designed for cost-effective, low-power, and low-noise applications. The architecture of v2.5 is built around a and one or more data lanes (typically 1 to 4, though the spec allows for more). Unlike parallel bus interfaces, this serial, differential approach reduces the number of pins, saves board space, and dramatically cuts power consumption. mipi d-phy specification v2.5 pdf
The v2.5 update focused on extending the reach and efficiency of the physical layer: Alternate Low Power (ALP): Page through the "PCB Guidelines" (often in an